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| W29C102 64K x 16 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K x 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C102 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES * Single 5-volt program and erase operations * Fast page-write operations * Low power consumption - 128 words per page - Page program cycle: 10 mS (max.) - Effective word-program cycle time: 39 S - Optional software-protected data write * Fast chip-erase operation: 50 mS * Read access time: 70/90/120 nS * Typical page program/erase cycles: 1K/10K * Ten-year data retention * Software and hardware data protection - Active current: 25 mA (typ.) - Standby current: 20 A (typ.) * Automatic program timing with internal VPP generation * End of program detection - Toggle bit - Data polling * Latched address and data * TTL compatible I/O * JEDEC standard word-wide pinouts * Available packages: 40-pin 600 mil DIP, TSOP and 44-pin PLCC -1- Publication Release Date: March 1998 Revision A3 W29C102 PIN CONFIGURATIONS NC CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 GND DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 BLOCK DIAGRAM VDD WE NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 V DD VSS CE OE WE CONTROL OUTPUT BUFFER 40-pin DIP 32 31 30 29 28 27 26 25 24 23 22 21 DQ0 . . DQ15 A0 A9 A10 A11 A12 A13 A14 A15 NC WE VDD NC CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 40-pin TSOP 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND . . A15 DECODER CORE ARRAY PIN DESCRIPTION DDD/ Q Q QC N N 13 14 15 E C C 6 5 4 3 2 1 V D D / WN EC AA 11 54 SYMBOL 39 38 37 36 PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection 44 43 42 41 40 DQ12 DQ11 DQ10 DQ9 DQ8 GND NC DQ7 DQ6 DQ5 DQ4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 A0-A15 DQ0-DQ15 CE OE WE VDD GND NC 44-pin PLCC 35 34 33 32 31 30 29 DDDD QQQQ 3210 /NAA OC01 E AAA 234 -2- W29C102 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C102 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29C102 is programmed on a page basis. Every page contains 128 words of data. If a word of data within a page is to be changed, data for the entire page must be loaded into the device. Any word that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the word-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the word-load cycle, the addresses are latched by the falling edge of either CE or WE, whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs first. If the host loads a second word into the page buffer within a word-load cycle time (TBLC) of 200 S, after the initial word-load cycle, the W29C102 will stay in the page load cycle. Additional words can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional word is loaded into the page buffer. A7 to A15 specify the page address. All words that are loaded into the page buffer must have the same page address. A0 to A6 specify the word address within the page. The words may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 words of data, are written simultaneously into the memory array. The typical programming time is 5 mS. The entire memory array can be written in 2.6 seconds. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-word program commands (with specific data to a specific address) to be performed before the data load operation. The three-word load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C102 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-word command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-word program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the -3- Publication Release Date: March 1998 Revision A3 W29C102 software data protection feature. To reset the device to unprotected mode, a six-word command sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram. Hardware Data Protection The integrity of the data stored in the W29C102 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7 & DQ15)- Write Status Detection The W29C102 includes a data polling feature to indicate the end of a programming cycle. When the W29C102 is in the internal programming cycle, any attempt to read DQ7 and/or DQ15 of the last word loaded during the page/word-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6 & DQ14)- Write Status Detection In addition to data polling, the W29C102 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 and/or DQ14 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address 0001H outputs the device code (004Fh). The product ID operation can be terminated by a three-word command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. -4- W29C102 TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V) MODE CE Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL OE VIL VIH X VIL X VIH VIH VIL VIL WE VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code 00DA (Hex) Device Code 004F (Hex) DQ. A0 = VIL; A1-A15 = VIL; A9 = VHH A0 = VIH; A1-A15 = VIL; A9 = VHH -5- Publication Release Date: March 1998 Revision A3 W29C102 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAAAH 5555H A0A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAAAH 5555H 8080H AAAAH 5555H 2020H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AAAA to address 5555 Software Data Protection Disable Flow Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 5555 to address 2AAA Load data A0A0 to address 5555 Load data 8080 to address 5555 (Optional page-load operation) Sequentially load up to 128 words of page data Load data AAAA to address 5555 Pause 10 mS Load data 5555 to address 2AAA Exit Load data 2020 to address 5555 Pause 10 mS Exit Notes for software program code: Data Format: DQ15-DQ0 (Hex) Address Format: A14-A0 (Hex) -6- W29C102 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAAAH 5555H 8080H AAAAH 5555H 1010H Software Chip Erase Acquisition Flow Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 8080 to address 5555 Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 1010 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ15-DQ0 (Hex) Address Format: A14-A0 (Hex) -7- Publication Release Date: March 1998 Revision A3 W29C102 Command Codes for Product Identification BYTE SEQUENCE ALTERNATE SOFTWARE (5) PRODUCT IDENTIFICATION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555H 2AAAH 5555H - SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H SOFTWARE PRODUCT IDENTIFICATION EXIT ADDRESS 5555H 2AAAH 5555H - DATA AAH 55H 90H - DATA AAH 55H 80H AAH 55H 60H DATA AAH 55H F0H - Pause 10 S Pause 10 S Pause 10 S Software Product Identification Acquisition Flow Product Identification Entry (1) Product Identification Mode (2, 3) Load data AAAA to address 5555 Product Identification Exit (1) Load data 5555 to address 2AAA Load data AAAA to address 5555 Load data 8080 to address 5555 Read address = 0 data = 00DA Load data 5555 to address 2AAA Load data AAAA to address 5555 Load data F0F0 to address 5555 Load data 5555 to address 2AAA Read address = 1 data = 004F Pause 10 S Load data 6060 to address 5555 (4) Normal Mode Pause 10 S Notes for software product identification: (1) Data format: DQ15-DQ0 (Hex); address format: A14-A0 (Hex). (2) A1-A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. (5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- W29C102 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except OE Transient Voltage (<20 nS ) on Any Pin to Ground Potential Voltage on A9 and OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER Power Supply Current SYM. ICC TEST CONDITIONS MIN. CE = OE = VIL, WE = VIH, all I/Os open Address inputs = VIL/VIH, at f = 5 MHz - LIMITS TYP. 25 MAX. 60 UNIT mA Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS ISB1 CE = VIH, all I/Os open Other inputs = VIL/VIH - 2 3 mA ISB2 CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/GND VIN = GND to VDD VOUT = GND to VDD IOL = 2.1 mA IOH = -0.4 mA - 20 200 A A A V V V V V ILI ILO VIL VIH VOL VOH 2.0 2.4 4.2 - 10 10 0.8 0.45 - VOH2 IOH = -100 A; VCC = 4.5V -9- Publication Release Date: March 1998 Revision A3 W29C102 Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pf pf AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load CONDITIONS 0V to 3.0V <5 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF for 90/120 nS CL = 30 pF for 70 nS AC Test Load and Waveform +5V 1.8K DOUT 100 pF for 90/120 nS 30 pF for 70 nS (Including Jig and Scope) 1.3K Input 3V 1.5V 0V Test Point Output 1.5V Test Point - 10 - W29C102 AC Characteristics, continued Read Cycle Timing Parameters (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change SYM. TRC TCE TAA TOE TCHZ TOHZ TOH W29C102-70 MIN. 70 0 MAX. 70 70 35 25 25 - W29C102-90 MIN. 90 0 MAX. 90 90 45 25 25 - W29C102-12 MIN. 120 0 MAX. 120 120 60 30 30 - UNIT nS nS nS nS nS nS nS Byte/Page-write Cycle Timing Parameters PARAMETER Write Cycle (erase and program) Address Setup Time Address Hold Time WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time SYMBOL TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC MIN. 0 50 0 0 0 0 70 70 100 50 0 TYP. MAX. 10 150 UNIT mS nS nS nS nS nS nS nS nS nS nS nS S Notes: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH. (b) Low level signal's reference level is VIL. - 11 - Publication Release Date: March 1998 Revision A3 W29C102 AC Characteristics, continued DATA Polling Characteristics (1) PARAMETER Data Hold Time OE Hold Time OE to Output Delay (2) Write Recovery Time SYMBOL TDH TOEH TOE TWR MIN. 10 10 0 TYP. MAX. UNIT nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. Toggle Bit Characteristics (1) PARAMETER Data Hold Time OE Hold Time OE to Output Delay (2) OE High Pulse Write Recovery Time SYMBOL TDH TOEH TOE TOEHP TWR MIN. 10 10 150 0 TYP. MAX. UNIT nS nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. - 12 - W29C102 TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A15-0 CE TCE OE TOE VIH WE TOH DQ15-0 High-Z Data Valid TAA Data Valid T CHZ T OHZ High-Z WE Controlled Write Cycle Timing Diagram TWC TAS Address A15-0 TAH CE TCS TOES TCH T OEH OE TWP TWPH WE TDS DQ15-0 Data Valid TDH Internal write starts - 13 - Publication Release Date: March 1998 Revision A3 W29C102 Timing Waveforms, continued CE Controlled Write Cycle Timing Diagram TAS TAH TWC Address A15-0 TCPH TCP CE TOES OE TOEH WE TDS DQ15-0 High Z Data Valid TDH Internal Write Starts Page Write Cycle Timing Diagram TWC Address A15-0 DQ15-0 CE OE TWP WE Word 0 TWPH TBLC Word 1 Word 2 Word N-1 Internal Write Start Word N - 14 - W29C102 Timing Waveforms, continued DATA Polling Timing Diagram Address A15-0 An An An An An WE CE TOEH OE TDH DQ7 or DQ15 TOE HIGH-Z TWR Toggle Bit Timing Diagram WE CE OE TOEH TDH TOE HIGH-Z TWR DQ6 or DQ14 Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of DQ6 and DQ14 may vary. 3. Any address location may be used but the address should not vary. - 15 - Publication Release Date: March 1998 Revision A3 W29C102 Timing Waveforms, continued Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Address A15-0 5555 2AAA 5555 Byte/page load cycle starts TWC DQ15-0 AAAA 5555 A0A0 CE OE WE TWP TWPH TBLC SW0 SW1 SW2 Word 0 Word N-1 Word N (last word) Internal write starts Reset Software Data Protection Timing Diagram Six-word sequence for resetting software data protection mode Address A15-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ15-0 AAAA 5555 8080 AAAA 5555 2020 CE OE WE TWP TWPH SW0 TBLC SW1 SW2 SW3 SW4 SW5 Internal programming starts - 16 - W29C102 Timing Waveforms, continued 5-Volt-only Software Chip Erase Timing Diagram Six-word code for 5V-only software chip erase Address A15-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ15-0 AAAA 5555 8080 AAAA 5555 1010 CE OE WE TWP TWPH SW0 TBLC SW1 SW2 SW3 SW4 SW5 Internal programming starts - 17 - Publication Release Date: March 1998 Revision A3 W29C102 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 70 90 120 POWER SUPPLY CURRENT MAX. (mA) 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 STANDBY VDD CURRENT MAX. (A) 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 600 mil DIP 600 mil DIP 600 mil DIP 40-pin TSOP (10 mm x 14 mm) 40-pin TSOP (10 mm x 14 mm) 40-pin TSOP (10 mm x 14 mm) 40-pin TSOP (10 mm x 20 mm) 40-pin TSOP (10 mm x 20 mm) 40-pin TSOP (10 mm x 20 mm) 44-pin PLCC 44-pin PLCC 44-pin PLCC 600 mil DIP 600 mil DIP 600 mil DIP 40-pin TSOP (10 mm x 14 mm) 40-pin TSOP (10 mm x 14 mm) 40-pin TSOP (10 mm x 14 mm) 40-pin TSOP (10 mm x 20 mm) 40-pin TSOP (10 mm x 20 mm) 40-pin TSOP (10 mm x 20 mm) 44-pin PLCC 44-pin PLCC 44-pin PLCC PACKAGE CYCLE W29C102-70 W29C102-90 W29C102-12 W29C102Q-70 W29C102Q-90 W29C102Q-12 W29C102T-70 W29C102T-90 W29C102T-12 W29C102P-70 W29C102P-90 W29C102P-12 W29C102-70B W29C102-90B W29C102-12B W29C102Q-70B W29C102Q-90B W29C102Q-12B W29C102T-70B W29C102T-90B W29C102T-12B W29C102P-70B W29C102P-90B W29C102P-12B Notes: 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 18 - W29C102 PACKAGE DIMENSIONS 40-pin PDIP Symbol Dimension in inches Dimension in mm Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090 Min. Nom. Max. 5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 52.20 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.37 0.36 52.58 15.49 13.97 2.79 3.56 15 17.02 2.29 D 40 21 A A1 A2 B B1 c D E E1 e1 L a E1 eA S 1 S Base Plane Seating Plane B B1 e1 eA 20 E c A A2 L A1 Notes: 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. a 44-pin PLCC HD D 6 1 44 40 Dimension in inches Dimension in mm Symbol 7 39 Min. Nom. Max. 0.185 0.020 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 Min. 0.51 3.68 0.66 0.41 0.20 Nom. Max. 4.70 3.81 0.71 0.46 0.25 3.94 0.81 0.56 0.36 16.71 16.71 16.00 16.00 E HE GE 17 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Notes: 0.648 0.653 0.658 16.46 16.59 0.648 0.653 0.658 16.46 16.59 0.050 BSC 1.27 0.590 0.610 0.630 14.99 15.49 0.590 0.610 0.630 14.99 15.49 0.680 0.690 0.700 17.27 0.680 0.690 0.700 17.27 0.090 0.100 0.110 0.004 2.29 BSC 17.53 17.78 17.53 17.78 2.54 2.79 0.10 L A2 A Seating Plane e GD b b1 A1 y 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. - 19 - Publication Release Date: March 1998 Revision A3 W29C102 Package Dimensions, continued 40-pin TSOP (10 mm x 14 mm) HD Dimension in Inches Dimension in mm D Symbol Min. Nom. Max. 0.047 Min. Nom. Max. 1.20 c 1 M e E A A1 A2 b c D E HD e L L1 Y 0.002 0.037 0.039 0.007 0.004 0.484 0.390 0.543 0.009 0.006 0.488 0.394 0.551 0.020 0.020 0.024 0.031 0.000 0 3 0.006 0.041 0.011 0.008 0.492 0.398 0.05 0.95 0.17 0.10 1.00 0.22 0.15 0.15 1.05 0.27 0.20 12.50 10.10 14.20 0.10(0.004) b 12.30 12.40 9.90 10 14.00 0.50 0.559 13.80 0.028 0.50 0.60 0.8 0.70 A L L1 A2 A1 Y 0.004 5 0.00 0 3 0.10 5 Controlling dimension: Millimeters 40-pin TSOP (10 mm x 20 mm) HD Dimension in Inches Dimension in mm Min. Nom. Max. 1.20 0.05 0.95 0.17 0.10 1.00 0.22 0.15 18.4 10 20.0 0.50 0.50 0.60 0.8 0.004 3 5 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.20 18.5 10.10 20.2 D Symbol Min. Nom. Max. 0.047 0.002 0.037 0.039 0.006 0.041 c 1 A A1 A2 b c D E HD e L L1 Y M e E 0.007 0.009 0.011 0.004 0.006 0.008 0.72 0.10(0.004) b 0.724 0.728 18.3 9.90 19.8 0.390 0.394 0.398 0.780 0.787 0.795 0.020 0.020 0.024 0.028 0.031 0.000 0 A L L1 A2 A1 Y Controlling dimension: Millimeters - 20 - W29C102 VERSION HISTORY VERSION A3 DATE Mar. 1998 PAGE 6 7 8 11 Add. pause 10 mS Add. pause 50 mS Correct the time from 10 mS to 10 S Change VDD from 5% to 10% for 70 nS DESCRIPTION Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 21 - Publication Release Date: March 1998 Revision A3 |
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